The present invention relates generally to the manufacture of semiconductor device, and more particularly, to a dual damascene process and structure for interconnect within an integrated circuit (IC) in a semiconductor device.
Multilayer conductor such as metal is generally formed within an IC during the manufacture of a semiconductor device. When the design rule of the semiconductor device is scaled down to under 1 xcexcm(micron), the multilayer conductor must be applied adaptively to the high density of the semiconductor device. Similarly, the size of the wiring structure also has to be shrunk adaptively to the smaller device size. More advanced wiring structure and new material are therefore required when IC technology is developed to the range of 0.25xcexcm. A dual damascene is thus used for such structure. The dual damascene process provides advantages of process simplification by decreasing steps of forming via holes and trenches, in which openings of metal layer wiring and via holes to connect with the underlying metal layers are produced at the same time, the procedure is advantageous to the lithography process and improves critical dimension (CD) control. Then metal is filled in the via holes and trenches by the same metal filling process, so that process steps are decreased.
Due to the simplification of steps implemented in the dual damascene process, the current use of aluminum (Al)/silicon dioxide (SiO2) system can be readily replaced with new materials for the dual damascene process. One of the new materials is copper (Cu). The use of Cu metalization can enhance signal transmission performance and reliability by aluminum. However, some problems hard to overcome are present when copper is applied for the Al prior art. For instance, a barrier layer is not needed between an Al metal wire and a SiO2 inter-metal dielectric (IMD) in a conventional Al interconnect structure, however, copper must be isolated from surrounding IMD when it is used, since copper is easy to diffuse/drift to adjacent dielectrics.
FIG. 1 shows a prior art process flow for a Cu self-aligned dual damascene. As shown in FIG. 1a, a barrier layer 12, a low dielectric constant layer 14, and an etch-stop layer 16 are formed in stack onto a copper region 10. A portion of the etch-stop layer 16 is removed with a photoresist 18 to serve as a mask to form an opening 20 to be that shown in FIG. 1b. In FIG. 1c, a second low dielectric constant layer 22 overlays on the intermediate etch-stop layer 16 and fills in the opening 20, and is overlaid with a bottom anti-reflection coating (BARC) 24. Then a photoresist 26 is patterned and used as a mask as shown in FIG. 1d, and an etching process is applied based on the pattern of the photoresist 26, in order to remove a portion of the BARC 24, the underlying second low dielectric constant layer 22 not covered with the photoresist 26, and the portion of the first low dielectric constant layer 14 through the opening 20 to the top surface of the barrier layer 12 to form a trench 28 and a via hole 29, as shown in FIG. 1e. After the photoresist 26 is removed, the exposed portion of the barrier layer 12 underneath the via hole 29 is removed to expose the copper region 10, as shown in FIG. 1f. The subsequent process is to fill in the trench 28 and the via hole 29 with a conductor (not shown in the figure) to connect to the underlying copper region 10.
Some problems exist in the above-described process. Although the dual damascene shown in FIG. 1 is a clean process since there is no photoresist in the via hole 29 and there is no concern of the crown-like fence over the via, high etching selectivity to the intermediate barrier 14 in open area and via bottom and high overlay accuracy on photoresist patterning for dual damascene etching are very concerned. It therefore requires a thicker etch-stop layer 16 and accurate trench-to-via photo alignment control. In actual process, a thick etch-stop layer 16 will increase the equivalent dielectric constant so as to be unable to meet the low dielectric constant requirement, resulting in the increase of RC delay and disadvantages to circuit performance. On the contrary, a thin etch-stop layer 16 will make optical path difference insufficient, resulting in a weak alignment signal for wafer alignment in the subsequent process, probably causing misjudgment on the alignment step and thereby misalignment of the trench 28 to the via hole 29, and thus increasing-resistance of the dual damascene structure. Based on same design rule, even though increasing etch selectivity of dielectric to etch-stop layer, the photo alignment signal is still weak. Furthermore, another disadvantage is contamination caused by the subsequent etching process. In FIG. 1f, exposed underlying copper region 10 will sputter up onto the sidewall of the via hole 29 to cause intra-layer metal line short when the exposed portion of the barrier layer 12 underneath the via hole 29 is etched.
It is therefore desired to provide a dual damascene process and structure to improve the trench-to-via alignment and out-diffusion of metal particles, such as copper.
An object of the present invention is to provide a dual damascene process and structure for out-diffusion prevention of metal particle such as copper, in which a liner deposition is applied before the barrier layer between the via and the underlying conductive region is etched. The liner on the sidewall of the via hole could be a barrier to sputtered species for the dielectric while particles are sputtered up from the conductive region onto the sidewall of the via hole during the removal step for the barrier layer on the conductive region.
Another object of the present invention is to provide a dual damascene process and structure including a liner deposition of a material with a different refractive index from that of the intermediate etch-stop layer covered by the liner in order to more clearly distinguish the interface of oxide-liner-oxide on the sidewall of the via and then to increase trench-to-via alignment accuracy.
A further object of the present invention is to provide a dual damascene process and structure to enhance signal for both broad band and laser alignment system by pull-back of the intermediate etch-stop layer between the stacked low dielectric constant layers to produce optical path difference for the subsequent photo alignment.
In one aspect of the present invention, a dual damascene process for a semiconductor device with a barrier layer, a first low dielectric constant layer, and a first etch-stop layer in stack thereof comprises depositing a liner after forming a via hole extending through the first etch-stop layer and the first low dielectric constant layer to a surface of the barrier layer, forming a second low dielectric constant layer, a second etch-stop layer or BARC, and a trench extending through the second etch-stop layer and the second low dielectric constant layer and connecting with the via hole, removing a portion of the barrier layer underneath the via hole, and filling in the trench and the via hole with a conductor after depositing a passivation layer such as Ta/TaN for a Cu region.
In another aspect of the present invention, a dual damascene process for a semiconductor device with a barrier layer, a first low dielectric constant layer, a first etch-stop layer, a second low dielectric constant layer, and a second etch-stop layer in stack thereof comprises depositing a liner after forming a via hole extending through the first etch-stop layer and the first low dielectric constant layer to a surface of the barrier layer and a trench extending through the second etch-stop layer and the second low dielectric constant layer and connecting with the via hole, removing a portion of the barrier layer underneath the via hole, and filling in the trench and the via hole with a conductor after depositing a passivation layer such as Ta/TaN for a Cu region.
According to the present invention, liner deposition and pull-back of intermediate etch-stop layer are provided for a dual damascene process and structure to prevent out-diffusion of metal such as copper from the via hole and improve photo alignment signal.
These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:
FIGS. 1a-1f shows a prior art process flow for a Cu self-aligned dual damascene;
FIGS. 2a-2f shows cross sectional views during a process flow for a dual damascene according to an embodiment of the present invention, in which a pull-back step for the intermediate etch-stop layer and a liner deposition for the first low dielectric constant layer are provided; and
FIGS. 3a to 3d show cross sectional views during a process flow for a dual damascene according to another embodiment of the present invention, in which a pull-back step for the intermediate etch-stop layer and a liner deposition for the first and second low dielectric constant layers are provided.